I don't understand why this doesn't work properly? Or do I have to write them all by hand? I'm trying to write a toy RISC V VM, but I feel that the way to process the instructions is too complicated (and the RISC V instruction set itself has a relatively fixed structure).

Syntax Error: expected COMMArust-analyzersyntax-error
Syntax Error: expected enum variantrust-analyzersyntax-error
Syntax Error: expected COMMArust-analyzersyntax-error
Syntax Error: expected enum variantrust-analyzersyntax-error
Syntax Error: expected COMMArust-analyzersyntax-error

macro_rules! r_type {
    ( $( $name:ident ),* ) => {
        $(
            #[doc = concat!("R型指令: ", stringify!($name))]
            $name {
                rd: String,
                rs1: String,
                rs2: String,
            },
        )*
    };
}

macro_rules! i_type {
    ( $( $name:ident ),* ) => {
        $(
            #[doc = concat!("I型指令: ", stringify!($name))]
            $name {
                rd: String,
                rs1: String,
                rs2: i64,
            },
        )*
    };
}

macro_rules! u_type {
    ( $( $name:ident ),* ) => {
        $(
            #[doc = concat!("U型指令: ", stringify!($name))]
            $name {
                rd: String,
                rs1: i64,
            },
        )*
    };
}
enum Instruction {
    // R 型
    r_type!(ADD, SUB, SLT, SLTU, AND, OR, XOR, SLL, SRL, SRA, MUL);

    // I 型
    i_type!(ADDI, SLTI, SLTIU, ANDI, ORI, XORI, SLLI, SRLI, SRAI);

    // U 型
    u_type!(LUI, AUIPC);

    // 伪指令
    SEQZ { rd: String, rs1: String },
    NOP,
    MV { rd: String, rs1: String },
    NOT { rd: String, rs1: String },
    Li { rd: String, rs1: i64 },
}

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